Rendering pipeline

Details Rendering pipeline Rendering pipeline

2007-01-30

2007-01-30

Jankus, Almis R. (Department: 2628)

Computer graphics processing and selective visual display system

Computer graphics processing

Three-dimension

C345S423000, C345S426000

Reexamination Certificate

active

10729874

ABSTRACT:
A rendering pipeline system for a computer environment uses screen space tiling (SST) to eliminate the memory bandwidth bottleneck due to frame buffer access and performs screen space tiling efficiently, while avoiding the breaking up of primitives. The system also reduces the buffering size required by SST. High quality, full-scene anti-aliasing is easily achieved because only the on-chip multi-sample memory corresponding to a single tile of the screen is needed. The invention uses a double-z scheme that decouples the scan conversion/depth-buffer processing from the more general rasterization and shading processing through a scan/z engine. The scan/z engine externally appears as a fragment generator but internally resolves visibility and allows the rest of the rendering pipeline to perform setup for only visible primitives and shade only visible fragments. The resulting reduced raster/shading requirements can lead to reduced hardware costs because one can process all parameters with generic parameter computing units instead of with dedicated parameter computing units. The invention processes both opaque and transparent geometries.

REFERENCES:
patent: 5886701 (1999-03-01), Chauvin et al.

Affiliated with

Also associated with

Rating

Rendering pipeline does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Rendering pipeline, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Rendering pipeline will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3823742