Read source line compensation in a non-volatile memory

Details Read source line compensation in a non-volatile memory Read source line compensation in a non-volatile memory

2007-02-20

2007-02-20

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S063000, C365S185200

Reexamination Certificate

active

11151168

ABSTRACT:
Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

REFERENCES:
patent: 4094008 (1978-06-01), Lockwood et al.
patent: 5335198 (1994-08-01), Van Buskirk et al.
patent: 6751131 (2004-06-01), Yamano
patent: 6754106 (2004-06-01), Wu et al.
patent: 6847561 (2005-01-01), Hashimoto et al.

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