Structure and method for parallel testing of dies on a...

Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element

Reexamination Certificate

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C324S754090, C324S1540PB

Reexamination Certificate

active

10340558

ABSTRACT:
In accordance with an embodiment of the present invention, a semiconductor wafer has a plurality of dies each having a circuit and a plurality of contact pads. The plurality of contact pads include a first contact pad to receive a power supply voltage, a second contact pad to receive a ground voltage, and a third contact pad to receive a test control signal. The third contact pad is connected to a programmable self-test engine (PSTE) embedded on the corresponding die so that the test control signal activates the PSTE to initiate a self-test. A probe card has a plurality of sets of probe pins, each set of probe pins having three probe pins for contacting the first, second, and third contact pads of one of a corresponding number of the plurality of dies. During wafer test, the plurality of sets of probe pins come in contact with a corresponding number of dies so that the self-test is carried out simultaneously in the corresponding number of dies.

REFERENCES:
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patent: 5929650 (1999-07-01), Pappert et al.
patent: 6323639 (2001-11-01), Park
patent: 6326801 (2001-12-01), Whetsel
patent: 6535009 (2003-03-01), Pochmuller
patent: 6550911 (2003-04-01), Park
patent: 6646461 (2003-11-01), Sugiura et al.
patent: 6658611 (2003-12-01), Jun
patent: 6696849 (2004-02-01), Ban et al.

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