Layout method and computer program product

Details Layout method and computer program product Layout method and computer program product

2007-07-17

2007-07-17

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S189011, C365S189040, C365S102000

Reexamination Certificate

active

11362926

ABSTRACT:
A required value of decoupling capacitance is calculated in advance for every functional cell, a virtual cell which has a functional cell, and a decoupling capacitance placing area required for placing the decoupling capacitance with the calculated value is created, the virtual cell is placed on a chip, and the decoupling capacitance cell is subsequently placed in the decoupling capacitance placing area of the virtual cell. A layout method of an integrated circuit and a computer program, in which a decoupling capacitance with an amount required for preventing malfunction caused by a noise can be surely placed, and there is no possibility that the functional cell will need to be replaced due to a shortage of the decoupling capacitance after placing the functional cell can be realized.

REFERENCES:
patent: 6882592 (2005-04-01), Noguchi et al.
patent: 6894926 (2005-05-01), Guterman et al.
patent: 2002-288253 (2002-10-01), None
patent: 2003-347405 (2003-12-01), None
patent: 2004-55954 (2004-02-01), None

Affiliated with

Also associated with

Rating

Layout method and computer program product does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Layout method and computer program product, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Layout method and computer program product will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3820507