Method and apparatus for a dual substrate package

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...

Reexamination Certificate

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C438S112000, C438S459000, C257SE21507

Reexamination Certificate

active

10676883

ABSTRACT:
A semiconductor die having a through via formed therein is disclosed. A first conductive layer is formed on the front side of the die and a second conductive layer is formed on the backside of the die, and coupled with the through via. A first package substrate is electrically coupled with the first conductive layer, and a second package substrate is electrically coupled with the second conductive layer. In another embodiment, a substrate ball electrically couples the first and second package substrates. In a further embodiment, a flip chip bump is attached to the first package substrate.

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Reche, J., “Wafer Thinning and Thru-Silicon Vias”, The Path to Wafer Level Packaging, 41 pages, Tru-Si Technologies, www.trusi.com, IEEE/CPMT Meeting, Santa Clara (CA) May 10, 2000.
PCT Search Report of International application No. PCT/US2004/032451, filed Sep. 29, 2004.

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