Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-06-26

2007-06-26

Mai, Son L. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S233500, C327S172000

Reexamination Certificate

active

11086444

ABSTRACT:
A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense amplifier circuit and data input/output ports; a control signal generation circuit configured to generate a plurality of control signals based on a reference clock signal externally supplied, the control signals serving for controlling data input and output of the sense amplifier circuit and data transferring timing in the data transfer circuit; and an internal clock signal generation circuit configured to generate an internal clock signal based on the reference clock signal for serving as the basis of the control signals, the internal clock signal having the same clock cycle as the reference clock signal and a constant duty ratio without regard to the duty ratio of the reference clock signal.

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patent: 2003-233992 (2003-08-01), None

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