Electrical computers and digital processing systems: processing – Processing architecture – Array processor
Reexamination Certificate
2007-05-01
2007-05-01
Kim, Kenneth S. (Department: 2111)
Electrical computers and digital processing systems: processing
Processing architecture
Array processor
C712S222000
Reexamination Certificate
active
10262195
ABSTRACT:
A method and apparatus for calculation and storage of Single-Instruction-Multiple-Data (SIMD) saturation history information pursuant to instruction execution. A coprocessor instruction has a format identifying a saturating operation, a first source having packed data elements and a second source having packed data elements. The saturating operation is executed on the packed data elements of the first and second sources. Saturation flags are stored in bits zero through seven of the Wireless Coprocessor Saturation Status Flag (wCSSF) register to indicate if a result of the saturating operation saturated.
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Aldrich Bradley C.
Paver Nigel C.
Kim Kenneth S.
Marvell International Ltd.
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