Semiconductor memory device with MOS transistors, each...

Details Semiconductor memory device with MOS transistors, each... Semiconductor memory device with MOS transistors, each...

2007-05-01

2007-05-01

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Floating gate

C365S185170, C365S189011, C365S230060

Reexamination Certificate

active

11087831

ABSTRACT:
A semiconductor memory device includes memory cells, a memory cell array, word lines, latch circuits, first row decoders, second row decoders, first isolating transistors, and second isolating transistors. The memory cell includes a memory cell transistor having a floating gate and a control gate. The memory cell array includes the memory cells arranged in a matrix. The word line connects in common the control gates of the memory cell transistors in a same row. The first row decoder applies a positive voltage to the word lines in a write operation and in an erase operation. The second row decoder applies a negative voltage to the word lines in a write operation and in an erase operation. The first isolating transistor switches between the first row decoder and the word line. The second isolating transistor switches between the second row decoder and the word line.

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patent: 2001-93288 (2001-04-01), None
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