Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

Details Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

2007-05-15

2007-05-15

Malsawma, Lex (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Thin active physical layer which is

Heterojunction

C257SE29193

Reexamination Certificate

active

10883443

ABSTRACT:
A semiconductor structure for use as a template for forming high-performance metal oxide semiconductor field effect transistor (MOSFET) devices is provided. More specifically, the present invention provides a structure that includes a SiGe-on-insulator substrate including a tensile-strained SiGe alloy layer located atop an insulating layer; and a strained Si layer atop the tensile-strained SiGe alloy layer. The present invention also provides a method of forming the tensile-strained SGOI substrate as well as the heterostructure described above. The method of the present invention decouples the preference for high strain in the strained Si layer and the Ge content in the underlying layer by providing a tensile-strained SiGe alloy layer directly atop on an insulating layer.

REFERENCES:
patent: 3602841 (1971-08-01), McGroddy
patent: 4665415 (1987-05-01), Esaki et al.
patent: 4853076 (1989-08-01), Tsaur et al.
patent: 4855245 (1989-08-01), Neppl et al.
patent: 4952524 (1990-08-01), Lee et al.
patent: 4958213 (1990-09-01), Eklund et al.
patent: 5006913 (1991-04-01), Sugahara et al.
patent: 5060030 (1991-10-01), Hoke
patent: 5081513 (1992-01-01), Jackson et al.
patent: 5108843 (1992-04-01), Ohtaka et al.
patent: 5134085 (1992-07-01), Gilgen et al.
patent: 5310446 (1994-05-01), Konishi et al.
patent: 5354695 (1994-10-01), Leedy
patent: 5371399 (1994-12-01), Burroughes et al.
patent: 5391510 (1995-02-01), Hsu et al.
patent: 5459346 (1995-10-01), Asakawa et al.
patent: 5471948 (1995-12-01), Burroughes et al.
patent: 5557122 (1996-09-01), Shrivastava et al.
patent: 5561302 (1996-10-01), Candelaria
patent: 5565697 (1996-10-01), Asakawa et al.
patent: 5571741 (1996-11-01), Leedy et al.
patent: 5592007 (1997-01-01), Leedy
patent: 5592018 (1997-01-01), Leedy
patent: 5670798 (1997-09-01), Schetzina
patent: 5679965 (1997-10-01), Schetzina
patent: 5683934 (1997-11-01), Candelaria
patent: 5840593 (1998-11-01), Leedy
patent: 5861651 (1999-01-01), Brasen et al.
patent: 5880040 (1999-03-01), Sun et al.
patent: 5940736 (1999-08-01), Brady et al.
patent: 5946559 (1999-08-01), Leedy
patent: 5960297 (1999-09-01), Saki
patent: 5989978 (1999-11-01), Peidous
patent: 6008126 (1999-12-01), Leedy
patent: 6025280 (2000-02-01), Brady et al.
patent: 6046464 (2000-04-01), Schetzina
patent: 6059895 (2000-05-01), Chu et al.
patent: 6066545 (2000-05-01), Doshi et al.
patent: 6090684 (2000-07-01), Ishitsuka et al.
patent: 6107143 (2000-08-01), Park et al.
patent: 6117722 (2000-09-01), Wuu et al.
patent: 6133071 (2000-10-01), Nagai
patent: 6165383 (2000-12-01), Chou
patent: 6221735 (2001-04-01), Manley et al.
patent: 6228694 (2001-05-01), Doyle et al.
patent: 6246095 (2001-06-01), Brady et al.
patent: 6255169 (2001-07-01), Li et al.
patent: 6261964 (2001-07-01), Wu et al.
patent: 6265317 (2001-07-01), Chiu et al.
patent: 6274444 (2001-08-01), Wang
patent: 6281532 (2001-08-01), Doyle et al.
patent: 6284623 (2001-09-01), Zhang et al.
patent: 6284626 (2001-09-01), Kim
patent: 6319794 (2001-11-01), Akatsu et al.
patent: 6361885 (2002-03-01), Chou
patent: 6362082 (2002-03-01), Doyle et al.
patent: 6368931 (2002-04-01), Kuhn et al.
patent: 6403486 (2002-06-01), Lou
patent: 6403975 (2002-06-01), Brunner et al.
patent: 6406973 (2002-06-01), Lee
patent: 6461936 (2002-10-01), Von Ehrenwall
patent: 6476462 (2002-11-01), Shimizu et al.
patent: 6493497 (2002-12-01), Ramdani et al.
patent: 6498358 (2002-12-01), Lach et al.
patent: 6501121 (2002-12-01), Yu et al.
patent: 6506652 (2003-01-01), Jan et al.
patent: 6509618 (2003-01-01), Jan et al.
patent: 6521964 (2003-02-01), Jan et al.
patent: 6531369 (2003-03-01), Ozkan et al.
patent: 6531740 (2003-03-01), Bosco et al.
patent: 6555839 (2003-04-01), Fitzgerald
patent: 6573126 (2003-06-01), Cheng et al.
patent: 6603156 (2003-08-01), Rim
patent: 6713326 (2004-03-01), Cheng et al.
patent: 6737670 (2004-05-01), Cheng et al.
patent: 6805962 (2004-10-01), Bedell et al.
patent: 6855436 (2005-02-01), Bedell et al.
patent: 6861158 (2005-03-01), Bedell et al.
patent: 2001/0009784 (2001-07-01), Ma et al.
patent: 2002/0074598 (2002-06-01), Doyle et al.
patent: 2002/0086472 (2002-07-01), Roberds et al.
patent: 2002/0086497 (2002-07-01), Kwok
patent: 2002/0090791 (2002-07-01), Doyle et al.
patent: 2002/0167048 (2002-11-01), Tweet et al.
patent: 2003/0032261 (2003-02-01), Yeh et al.
patent: 2003/0040158 (2003-02-01), Saitoh
patent: 2003/0057184 (2003-03-01), Yu et al.
patent: 2003/0067035 (2003-04-01), Tews et al
patent: 2003/0139000 (2003-07-01), Bedell et al.
patent: 2003/0172866 (2003-09-01), Hsu et al.
patent: 2004/0018701 (2004-01-01), Ueda
patent: 2004/0053477 (2004-03-01), Ghyselen et al.
patent: 2004/0075141 (2004-04-01), Maeda et al.
patent: 2004/0075143 (2004-04-01), Bae et al.
patent: 2004/0087114 (2004-05-01), Xiang et al.
patent: 2004/0178406 (2004-09-01), Chu
patent: 2004/0206950 (2004-10-01), Suvkhanov et al.
patent: 2004/0242006 (2004-12-01), Bedell et al.
patent: 2005/0003229 (2005-01-01), Bedell et al.
patent: 2005/0017236 (2005-01-01), Sugii et al.
patent: 0 967 636 (1999-12-01), None
patent: 1 174 928 (2002-01-01), None
patent: 1-162362 (1989-06-01), None
patent: WO 94/27317 (1993-05-01), None
patent: WO 02/454156 (2002-06-01), None
Rim, et al., “Transconductance Enhancement in Deep Submicron Strained-Sin-MOSFETs”, International Electron Devices Meeting, 26, 8, 1, IEEE, Sep. 1998.
Rim, et al. “Characteristics and Device Design of Sub-100 nm Strained Si N- and PMOSFETs”, 2002 Symposium On VLSI Technology Digest of Technical Papers, IEEE, pp. 98-99.
Scott, et al. “NMOS Drive Current Reduction Caused by Transistor Layout and Trench Isolation Induced Stress”, International Electron Devices Meeting, 34.4.1, IEEE, Sep. 1999.
Ootsuka, et al. “A Highly Dense, High-Performance 130nm node CMOS Technology for Large Scale System-on-a-Chip Application”, International Electron Device Meeting, 23.5.1, IEEE, Apr. 2000.
Ito, et al. “Mechanical Stress Effect of Etch-Stop Nitride and its Impact on Deep Submicron Transistor Design”, International Electron Devices Meeting, 10.7.1, IEEE, Apr. 2000.
Shimizu, et al. “Local Mechanical-Stress Control (LMC): A New Technique for CMOS-Performance Enhancement”, International Electron Devices Meeting, IEEE, Mar. 2001.
Ota, et al. “Novel Locally Strained Channel Technique for high Performance 55nm CMOS”, International Electron Devices Meeting, 2.2.1, IEEE, Feb. 2002.
Ouyang, et al. “Two-Dimensional Bandgap Engineering in a Novel Si/SiGe pMOSFETS With Enhanced Device Performance and Scalability”, Microelectronics Research Center, pp. 151-154, 2000 IEEE.
Sayama et al., “Effect of <Channel Direction for High Performance SCE Immune pMOSFET with Less Than 0.15um Gate Length”ULSI Development Center, pp. 27.5.1-27.5.4, 1999 IEEE.

Affiliated with

Also associated with

Rating

Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI), we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI) will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3816533