Semiconductor integrated circuit verification system

Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation

Reexamination Certificate

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C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C703S015000, C703S019000, C703S017000, C714S036000, C714S030000, C714S031000, C702S066000, C702S070000, C702S074000

Reexamination Certificate

active

10884251

ABSTRACT:
An aspect of the present invention provides a semiconductor integrated circuit verification system that includes a compiler configured to receive circuit descriptions of a semiconductor integrated circuit to be verified and create a circuit database, a circuit analysis unit configured to receive the circuit database to analyze the circuitry inside the semiconductor integrated circuit based on the circuit database, the circuit analysis unit configured to determine the timing at which the abstraction level of the circuit is switched and generate a simulation object, and a simulation execution unit configured to receive the simulation object and conduct a simulation of the semiconductor integrated circuit based on the simulation object.

REFERENCES:
patent: 5220512 (1993-06-01), Watkins et al.
patent: 5535223 (1996-07-01), Horstmann et al.
patent: 5862149 (1999-01-01), Carpenter et al.
patent: 6059451 (2000-05-01), Scott et al.
patent: 6067650 (2000-05-01), Beausang et al.
patent: 6170072 (2001-01-01), Moriguchi et al.
patent: 6449755 (2002-09-01), Beausang et al.
patent: 6678871 (2004-01-01), Takeyama et al.
patent: 6701504 (2004-03-01), Chang et al.
patent: 6988232 (2006-01-01), Ricchetti et al.
patent: 2002/0073380 (2002-06-01), Cooke et al.
patent: 2002/0166098 (2002-11-01), Chang et al.
patent: 2003/0009727 (2003-01-01), Takeyama et al.
patent: 2003/0023941 (2003-01-01), Wang et al.
patent: 2003/0149949 (2003-08-01), Price et al.
patent: 2004/0148150 (2004-07-01), Ashar et al.
patent: 2005/0015691 (2005-01-01), Nozuyama
patent: 2005/0229123 (2005-10-01), Wang et al.
patent: 2006/0107160 (2006-05-01), Ricchetti et al.
Wolfgang Meyer, Raul Camposano□□Fast Hierachical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy□□30 ACM/IEEE Design Automation Conference, 1993 ACM 0-89791-577-1/93/0006-0515.
Robert Chen, James Coffman□□Multi-Sim, A Dynamic Multi-Level Simulator□□Proceedings of the 15th Conference on Design Automation, Jun. 1978.

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