Normally off JFET

Details Normally off JFET Normally off JFET

2007-02-20

2007-02-20

Jackson, Jerome (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C237S049000, C237S049000, C237S049000, C237S049000, C438S186000

Reexamination Certificate

active

11053312

ABSTRACT:
A normally off JFET is formed by the implantation of a P base; and a shallower P island atop the P base, forming a narrow lateral conduction channel between the two and a shallow gate implant in the device top surface which forms a second lateral conduction channel with the island. The two channels are each less than 0.5 microns thick and have an impurity concentration such that the channels are depleted at zero gate voltage and are turned on when the gate is forward biased. The gate surrounds a source implant region and a remote drain is provided which is connected to the top surface of the device for a lateral JFET or the bottom of the device for a vertical conduction JFET.

REFERENCES:
patent: 5378642 (1995-01-01), Brown et al.
patent: 5889298 (1999-03-01), Plumton et al.
patent: 6207994 (2001-03-01), Rumennik et al.
patent: 6307223 (2001-10-01), Yu
patent: 6459108 (2002-10-01), Bartsch et al.
patent: 6674107 (2004-01-01), Yu
patent: 2002/0167011 (2002-11-01), Kumar et al.
patent: 2003/0168704 (2003-09-01), Harada et al.

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