Logic process DRAM

Details Logic process DRAM Logic process DRAM

2007-02-27

2007-02-27

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S072000, C365S051000, C365S189020, C365S230020

Reexamination Certificate

active

11138681

ABSTRACT:
A dynamic random access memory (DRAM) unit includes pluralities of bit line pairs and word lines. Each bit line pair includes first and second bit lines aligned with each other in an end-to-end arrangement. The first bit lines are arranged substantially parallel and consecutively adjacent to one another. The second bit lines are arranged substantially parallel and consecutively adjacent to one another. Each word line is associated with either the first bit lines or the second bit lines. A first array is formed by the first bit lines and the associated word lines. A second array is formed by the second bit lines and the associated word lines. Each of a plurality of memory cells is associated with every other bit line along each word line. Each of a plurality of multiplexers is in communication with two adjacent bits lines within one of the first and second arrays.

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