Frequency divider circuit with controllable frequency...

Details Frequency divider circuit with controllable frequency... Frequency divider circuit with controllable frequency...

2007-11-20

2007-11-20

Nguyen, Linh My (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S117000

Reexamination Certificate

active

11513655

ABSTRACT:
A frequency divider circuit is disclosed with at least one push-pull divider with adjustable division ratio and a connected converter device. The circuit converts a clock signal delivered by a push-pull divider into a single-ended signal. A first and a second single-ended divider are connected to the output of the converter device, and a feedback path is provided, which is connected to the output of the push-pull divider and to the outputs of the first and of the at least one second single-ended divider, and which includes an evaluation circuit. This circuit has first and second inputs which are connected to the first and second single-ended dividers in such a way that a future state of the clock signal delivered by the single-ended divider in question can be supplied to the inputs of the evaluation circuit. The evaluation circuit evaluates states of the clock signals delivered by the first and second single-ended dividers, i.e., states which will not exist until after future switching functions have been performed. As a result, additional time is gained for converting the signal to be divided from a push-pull signal to a single-ended signal.

REFERENCES:
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“A CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver”, Hamid R. Rategh, Hirad Samavati and Thomas H. Lee, IEEE Journal On Solid-State Circuits, vol. 35, No. 5, May 2000, 8 pgs.
“A 27-mW CMOS Fractional-NSynthesizer Using Digital Compensation for 2.5-Mb/s GFSK Modulation”, Michael H. Perrott, Theodore L. Tewksbury III and Charles G. Sodini, IEEE Journal Of Solid-State Circuits, vol. 32, No. 12, Dec. 1997, 13 pgs.

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