Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2007-07-03

2007-07-03

Phung, Anh (Department: 2824)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S063000, C365S094000, C365S190000

Reexamination Certificate

active

11142863

ABSTRACT:
In a memory cell array in a hierarchical bit line mode in which sub-arrays in a virtual ground line mode are arranged in a column direction, data is read out at high speed, preventing fluctuation in wiring capacity of a main bit line. In each sub-array, one of a source electrode or a drain electrode in each of the memory cells in the same column is connected to a common first bit line, and the other thereof is connected to a second bit line. The first bit lines of one half of the sub-arrays positioned in the same column are connected to the first main bit line through selection transistors and the second bit lines thereof are connected to the second main bit line through selection transistors, and the first bit lines of the other half of the sub-arrays positioned in the same column are connected to the second main bit line through selection transistors and the second bit lines thereof are connected to the first main bit line through selection transistors.

REFERENCES:
patent: 5202848 (1993-04-01), Nakagawara
patent: 2005/0265107 (2005-12-01), Tanaka
patent: 3-179775 (1991-08-01), None
patent: 10-11991 (1998-01-01), None
patent: WO-03/044868 (2003-05-01), None

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