Mixing prevention circuit for preventing mixing of...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

Reexamination Certificate

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Details

C327S603000

Reexamination Certificate

active

11346272

ABSTRACT:
First, second, and third inverters are connected in series. An output of the third inverter is supplied to the gates of first pMOS and nMOS. An output of the first inverter is supplied to the gate of the second nMOS and the drain of the second nMOS is connected to the source of the first nMOS. The drains of the second pMOS, third nMOS are supplied with the output of the first inverter and the gates thereof are supplied with the output of the third inverter. The gate of the third pMOS is connected to the drains of the first nMOS and pMOS and the drain thereof is connected to the source of the second pMOS. The gate of the fourth nMOS is connected to the drains of the first nMOS and pMOS and the drain thereof is connected to the source of the third nMOS.

REFERENCES:
patent: 5541536 (1996-07-01), Rajivan
patent: 6515532 (2003-02-01), Jinzai
patent: 6870412 (2005-03-01), Cho
patent: 64-84637 (1989-03-01), None
Toshiba Corp. Semiconductor Co., p. 83, “Toshiba Very High Speed C2MOS TC74VCH-VHCT Series Data Book”, 1999.
Toshiba Corp. Semiconductor Co., p. 871, “Low Voltage C2MOS Logic TC74VCX/LCX/LVX Series Data Book”, 2001.

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