Charge pump circuit for generating high voltages required in...

Static information storage and retrieval – Powering

Reexamination Certificate

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C365S229000, C327S536000

Reexamination Certificate

active

11050753

ABSTRACT:
Different stepped-up voltages and different output currents are generated in one charge pump circuit without increasing the chip area of the charge pump circuit and also electric power consumption in the charge pump circuit to be reduced to a very low power consumption level in standby mode and other modes. A semiconductor integrated circuit device comprises one charge pump circuit with an N number of basic pump cell stages connected to step up voltages in the erase and write modes of a non-volatile memory or the like, generates stepped-up voltages lower than in the erase and write modes and different from one another in output current supply capability, by using series- or parallel-connected pump cells not in excess of the N number of pump cell stages mentioned above, and changes a voltage step-up clock to a stepped-up voltage detection signal.

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patent: 6121821 (2000-09-01), Miki
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patent: 6891764 (2005-05-01), Li
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patent: 2004/0095806 (2004-05-01), Osawa et al.
patent: 60-095794 (1985-05-01), None
patent: 61-077197 (1986-04-01), None
patent: PCT/WO 97/12369 (1997-04-01), None
patent: WO 2004/047274 (2004-06-01), None
T. Tanzawa and T. Tanaka, “A dynamic analysis of the Dickson charge pump circuit;” IEEE J. Solid-State Circuits, vol. 32, No. 8, pp. 1231-1240, Aug. 1997.

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