Multi-channel serdes receiver for chip-to-chip and backplane...

Details Multi-channel serdes receiver for chip-to-chip and backplane... Multi-channel serdes receiver for chip-to-chip and backplane...

2007-01-02

2007-01-02

Tran, Khanh (Department: 2611)

Pulse or digital communications

Receivers

Angle modulation

Reexamination Certificate

active

09955424

ABSTRACT:
A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes: (1) a PLL-based central frequency synthesizer and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer, each of the plurality including a clock recovery system having a phase detector and a phase interpolator, the clock recovery system coupling the phase detector and the central frequency synthesizer.

REFERENCES:
patent: 5184092 (1993-02-01), Shahriary et al.
patent: 5457423 (1995-10-01), Hegeler
patent: 5651031 (1997-07-01), Ishizu
patent: 5726596 (1998-03-01), Perez
patent: 6018547 (2000-01-01), Arkhipkin et al.
patent: 6552619 (2003-04-01), Shastri
patent: 6586977 (2003-07-01), Yang et al.
patent: 6687319 (2004-02-01), Perino et al.
patent: RE38482 (2004-03-01), Leung et al.
patent: 6795695 (2004-09-01), Brekelmans et al.

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