Delay-locked loop having a pre-shift phase detector

Details Delay-locked loop having a pre-shift phase detector Delay-locked loop having a pre-shift phase detector

2007-07-03

2007-07-03

Nguyen, Viet Q. (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C327S147000, C327S146000, C327S149000, C327S158000, C327S161000, C327S153000, C327S159000

Reexamination Certificate

active

11345552

ABSTRACT:
A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

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Micron Technology, Inc., “DDR SDRAM Functionality and Controller Read Data Capture”, Design Line, vol. 8, Issue 3, 3Q99, 1999. 24 pages.

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