Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2007-07-10
2007-07-10
Estrada, Michelle (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C257S755000, C257SE21530, C257SE21232, C438S105000
Reexamination Certificate
active
11176024
ABSTRACT:
A process for defining and controlling the mask height of sensor devices is disclosed. An RIE-resistant, image layer, such as Cu or NiFe, is deposited after the DLC layer. A combination of RIE and ion milling processes or reactive ion beam etching processes are used to form the mask structure. Having an RIE-resistant layer precisely defines the DLC edge and minimizes the line edge roughness that result from fast removal of duramide during RIE. This solution controls the formation of the edges of the sensors and provides good definition for DLC mask edges. The image layer may be chemical mechanical polished to eliminate ion milling before the final RIE step.
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Bracewell & Giuliani LLP
Estrada Michelle
Hitachi Global Storage Technologies Netherlands BV
Stark Jarrett J.
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