Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2007-05-22
2007-05-22
Phan, Trong (Department: 2827)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230080, C365S233100
Reexamination Certificate
active
10854554
ABSTRACT:
A memory (10) has a plurality of memory cells, a transceiver (56) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differential data signal. The memory (10) can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is scored in the memory array (14) by interleaving in multiple sub-arrays (15, 17). During a hidden refresh mode of operation, one sub-array (15) is accessed while another sub-array (17) is refreshed. Two or more of the memories (10) may be chained together to provide a high speed low power memory system.
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Greaves Carlos A.
Pelley Perry H.
Freescale Semiconductor Inc.
Hill Daniel D.
Phan Trong
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