Register read for volatile memory

Details Register read for volatile memory Register read for volatile memory

2007-07-31

2007-07-31

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S222000, C710S035000, C710S061000, C369S047480, C327S041000, C257S068000

Reexamination Certificate

active

11623349

ABSTRACT:
Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2′b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.

REFERENCES:
patent: 6401213 (2002-06-01), Jeddeloh
patent: 6728798 (2004-04-01), Roohparvar
patent: 7096283 (2006-08-01), Roohparvar
patent: 2005/0060481 (2005-03-01), Belonoznik

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