Patent
1984-05-09
1986-11-11
Clawson, Jr., Joseph E.
357 238, 357 39, 357 52, H01L 2978
Patent
active
046225684
ABSTRACT:
Lateral planar FET structure (2) is disclosed for bidirection power switching, including AC application. Voltage blocking capability is enhanced in the lateral current flow device (2) by field shaping in the drift region (22). In the OFF state, the field shaping region (24) straightens field lines and prevents gradient induced depletion and unwanted inversion of conductivity type along a lateral drift region portion (54) extending beneath a top major surface (28) of the substrate between channel-containing regions (6) and (8).
REFERENCES:
patent: 4199774 (1980-04-01), Plummer
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patent: 4300150 (1981-11-01), Colak
patent: 4409606 (1983-10-01), Wagenaar et al.
patent: 4498094 (1985-02-01), Houthoff et al.
High Voltage Thin Layer Devices (Resurf Devices), J. A. Appels & H. M. J. Vaes, Philips Research Laboratories, Eindhoven--The Netherlands, International Electron Device Meeting Technical Digest, 1979, pp. 238-241 (CH1504-0/79/0000-0238$00.75).
Lateral DMOS Power Transistor Design, S. Colak, B. Singer, E. Stupp, IEE Electron Device Letters, vol. EDL-1, No. 4, Apr. 1980, pp. 51-53 (0193-8576/80/0400-0051$00.75).
G. Feth et al., "Planar Trial Structures," IBM Tech Discl. Bull., vol. 19 #6, Nov. 1976, pp. 2297-2301.
Benjamin James A.
Lade Robert W.
Schutten Herman P.
Clawson Jr. Joseph E.
Eaton Corporation
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