Two-bit offset cancelling A/D converter with improved common...

Details Two-bit offset cancelling A/D converter with improved common... Two-bit offset cancelling A/D converter with improved common...

2007-01-30

2007-01-30

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C326S080000

Reexamination Certificate

active

11271729

ABSTRACT:
A two-bit offset canceling A/D converter with improved common mode rejection and threshold sensitivity for use in GPS receivers. A device in accordance with the present invention comprises a level shifter, the level shifter receiving a positive signal and a negative signal, the level shifter shifting the positive signal and the negative signal such that a difference between the positive signal and the negative signal is larger than a threshold value, and a comparator, coupled to the level shifter, the comparator providing as outputs of the comparators a sign bit and two magnitude bits wherein the comparator comprises a plurality of switched capacitor amplifiers.

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F. Kaess et al., “High-Speed GaAs Comparators for Low-Power 8-bit ADCs”, 1998 IEEE, pp. WT11-4.1-WT11-4.4.
H. Elwan et al., “CMOS low power baseband chain for a GSM/DECT multistandard receiver”, IEE Proc.-Circuits Devices Syst., vol. 149, No. 516, pp. 337-347, Oct./Dec. 2002.

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