Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates
Reexamination Certificate
2007-09-25
2007-09-25
Fourson, George R. (Department: 2823)
Semiconductor device manufacturing: process
Bonding of plural semiconductor substrates
C438S406000, C438S459000, C438S479000, C257SE21122, C257SE21567, C257SE21569
Reexamination Certificate
active
11218201
ABSTRACT:
The invention encompasses a method of forming a semiconductor-on-insulator construction. A substrate is provided. The substrate includes a semiconductor-containing layer over an insulative mass. The insulative mass comprises silicon dioxide. A band of material is formed within the insulative mass. The material comprises one or more of nitrogen argon, fluorine, bromine, chlorine, iodine and germanium.
REFERENCES:
patent: 5071785 (1991-12-01), Nakazato et al.
patent: 5468657 (1995-11-01), Hsu
patent: 5516707 (1996-05-01), Loh et al.
patent: 5767548 (1998-06-01), Wonderak et al.
patent: 5795813 (1998-08-01), Hughes et al.
patent: 6071791 (2000-06-01), Hughes et al.
patent: 6144072 (2000-11-01), Iwamatsu et al.
patent: 6249026 (2001-06-01), Matsumoto et al.
patent: 6410938 (2002-06-01), Xiang
patent: 6509613 (2003-01-01), En et al.
patent: 6596570 (2003-07-01), Furukawa
patent: 6958282 (2005-10-01), Huttner et al.
patent: 6992355 (2006-01-01), Mouli
patent: 2001/0039098 (2001-11-01), Lu
patent: 2002/0145174 (2002-10-01), Aipperspach et al.
patent: 2003/0189229 (2003-10-01), Mouli
patent: 2004/0108566 (2004-06-01), Himi et al.
patent: 2004/0175899 (2004-09-01), Lu et al.
patent: 2006/0003562 (2006-01-01), Mouli
“Novel NICE (Nitrogen Implantation into CMOS Gate Electrode and Source-Drain) Structure for High Reliability and High Performance . . . ”; T. Kuroi et al.; 1993 IEEE; pp. 13.2.1-13.2.4.
“Dopant Redistribution in SOI during RTA: A Study on Doping in Scaled-down SI Layers”; Heemyong Park et al; 1999 IEEE.
Fourson George R.
Maldonado Julio J.
Micro)n Technology, Inc.
Wells St. John P.S.
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