Widening jitter margin for faster input pulse

Details Widening jitter margin for faster input pulse Widening jitter margin for faster input pulse

2007-05-08

2007-05-08

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Rectangular or pulse waveform width control

C327S172000

Reexamination Certificate

active

11231412

ABSTRACT:
A pulse delay circuit induces lager jitter to faster input reference pulse trains than before. A buffer receives a reference pulse train and provides non-inverted and inverted pulses. Low pass filters (LPF) and comparators receive the non-inverted and inverted pulses from the buffer and provide pulses having delayed leading and trailing edges. Dividers divide the delayed pulses by 2 to produce the respective pulse trains having a half frequency. An XOR gate produces an exclusive OR of the delayed and divided pulse trains to provide a pulse train having delayed leading and/or trailing edges relative to the reference pulse train. If the delays by the LPFs and comparators are changed, the output pulses from the XOR gate have jitter.

REFERENCES:
patent: 5889435 (1999-03-01), Smith et al.
patent: 6518809 (2003-02-01), Kotra
patent: 6737927 (2004-05-01), Hsieh
patent: 6998893 (2006-02-01), Takahashi et al.

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