Programmable receive-side channel equalizer

Details Programmable receive-side channel equalizer Programmable receive-side channel equalizer

2007-01-16

2007-01-16

Vo, Don N. (Department: 2611)

Pulse or digital communications

Equalizers

C333S02800T

Reexamination Certificate

active

10348871

ABSTRACT:
A digitally programmable analog receive-side channel equalizer includes N identical zero-positioning (ZP) circuit pairs in a cascade, where the transfer function of one ZP circuit of each pair exhibits a positive zero and the transfer function of the other ZP circuit exhibits a negative zero. By digitally controlling tunable capacitors within the pairs, the equalizer's frequency response and gain can be adjusted, while a controllable (e.g., constant) group delay is maintained. The number of blocks in the cascade can be selected, and each block independently configured, to optimally compensate for high-frequency losses in a wide range of transmission environments. One implementation involves a T-block cascade with output taps that feed a T:1 output selector such that the output of the overall equalizer can be selected to be any one of these taps corresponding to a programmable equalizer of effective length N where N≦T.

REFERENCES:
patent: 6300849 (2001-10-01), Takeda
patent: 6362681 (2002-03-01), Bollati et al.
patent: 2003/0020551 (2003-01-01), Henkel
patent: 2003/0095005 (2003-05-01), Morie et al.

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