Method of controlling page buffer having dual register and...

Details Method of controlling page buffer having dual register and... Method of controlling page buffer having dual register and...

2007-09-11

2007-09-11

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S185080, C365S189050

Reexamination Certificate

active

11008362

ABSTRACT:
Disclosed are a method of controlling a page buffer having a dual register and a control circuit thereof. In the present invention, during a normal program operation, a normal program operation is performed through the same transmission path as a data transmission path along which data is outputted from bit lines of a memory cell array to a YA pad according to a signal PBDO used in a read operation. A program operating time can be reduced and the whole program operation of a chip can be thus reduced. It is also possible to reduce current consumption by shortening a data path during the normal program operation.

REFERENCES:
patent: 6671204 (2003-12-01), Im
patent: 6813184 (2004-11-01), Lee
patent: 6963509 (2005-11-01), Ju
patent: 7042770 (2006-05-01), Lee et al.
patent: 7061813 (2006-06-01), Lee
patent: 7149130 (2006-12-01), Lee
patent: 2003/0117856 (2003-06-01), Lee et al.
patent: 20030011234 (2003-02-01), None
patent: 20050101874 (2005-10-01), None

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