Multi-bit virtual-ground NAND memory device

Details Multi-bit virtual-ground NAND memory device Multi-bit virtual-ground NAND memory device

2007-09-18

2007-09-18

Phan, Trong (Department: 2827)

Static information storage and retrieval

Floating gate

Multiple values

C365S185160, C365S185170, C365S185290

Reexamination Certificate

active

11119376

ABSTRACT:
An array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot hole injection. A write voltage is applied by a bitline to two NAND chains in series. The subsequent bitline on the side of the memory cell to be programmed is maintained on floating potential, whereas the bitline on the other side is set to an inhibit voltage, which is provided to inhibit a program disturb of an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density.

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