Delta sigma modulator analog-to-digital converters with...

Details Delta sigma modulator analog-to-digital converters with... Delta sigma modulator analog-to-digital converters with...

2007-05-22

2007-05-22

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S155000

Reexamination Certificate

active

11388425

ABSTRACT:
The analog-to-digital (ADC) delta sigma modulators in the signal processing systems described utilize comparator number reduction techniques to improve a delta sigma modulator quantizer. The delta sigma modulator generates one quantization output signal per delta sigma modulator output cycle. A quantizer of the delta sigma modulator includes one or more comparators, that each makes at least two comparisons per delta sigma modulator output cycle. The one or more comparators compare a quantizer input signal against one or more thresholds. A successive reference generator determines the one or more thresholds for the one or more comparators wherein each of the one or more thresholds during a later one of the at least two comparisons is in conformity with results of an earlier one of the at least two comparisons. Redundant and other iterative comparison techniques and threshold generation techniques are used to efficiently reduce the number of comparators in the quantizer while maintaining accuracy.

REFERENCES:
patent: 5870052 (1999-02-01), Dedic et al.
patent: 6215427 (2001-04-01), Bonhoure et al.
patent: 6380881 (2002-04-01), Harada et al.
patent: 6717542 (2004-04-01), Harada
patent: 6809674 (2004-10-01), Ramsden
patent: 6919837 (2005-07-01), Harada et al.
patent: 2006/0077090 (2006-04-01), Schimper

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