Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2007-05-01
2007-05-01
Awad, Amr A. (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S095000
Reexamination Certificate
active
10613212
ABSTRACT:
A pixel has first to third N-type TFT elements serially connected between a data line and a pixel electrode node. Each gate of the first and second TFT elements is connected to a first gate line, while the gate of the third TFT element is connected to a second gate line. The first and second gate lines in a select state each set to a high voltage that can fully turn-on the first to third TFT elements. The first gate line in a non-select state is set to a low voltage that can fully turn-off the first and second TFT elements, while the second gate line in the non-select state is set to an intermediate voltage between the maximum and the minimum voltages being transmitted on the data line.
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Awad Amr A.
Boddie William L
McDermott Will & Emery LLP
Mitsubishi Denki & Kabushiki Kaisha
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