Image processor with noise reduction circuit

Details Image processor with noise reduction circuit Image processor with noise reduction circuit

2007-09-04

2007-09-04

Vu, Ngoc-Yen (Department: 2622)

Television

Camera, system and detail

Combined image signal generator and general image signal...

C348S222100

Reexamination Certificate

active

10634338

ABSTRACT:
A digital imaging system includes an image sensor, an interface circuit, a frame buffer and an image processor. The image sensor includes a two-dimensional array of pixel elements and outputs digital signals on a pixel bus as pixel data representing an image of a scene. The interface circuit is coupled to receive the pixel data from the pixel bus. The frame buffer is coupled to store pixel data provided by the interface circuit. The image processor operates to process the pixel data stored in the frame buffer to generate image data for displaying the image of the scene. The interface circuit includes a noise reduction circuit operated to perform signal processing on the pixel data received on the pixel bus for noise reduction. Thus, random noise such as readout noise can be eliminated as pixel data are being transferred from the image sensor and stored in the frame buffer.

REFERENCES:
patent: 6753910 (2004-06-01), Ogata et al.
patent: 7123294 (2006-10-01), Uchikawa
Xinqiao Liu and Abbas El Gamal, “Photocurrent Estimation from Multiple Non-destructive Samples in a CMOS Image Sensor”, Proceedings of the SPIE Electronic Imaging 2001 Conference, vol. 4306, San Jose, CA (Jan. 2001), 9 pages.

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