Prescaler

Details Prescaler Prescaler

2007-07-24

2007-07-24

Lam, Tuan (Department: 2816)

Electrical pulse counters, pulse dividers, or shift registers: c

Systems

Pulse multiplication or division

C377S048000, C327S115000, C327S117000

Reexamination Certificate

active

10908074

ABSTRACT:
Disclosed is a Dual-Modulus Prescaler (DMP) dividing an input signal into an output signal, comprising: a synchronous counter, including a D-Flip-Flop (DFF), a first NOR-Flip-Flop and a second NOR-Flip-Flop, receiving the input signal, the division ratio thereof being based on an intermediate signal; a control logic, controlling the division ratio of the synchronous counter and selecting the output frequency based on first and second control signals, and outputting the intermediate signal to the synchronous counter; and an asynchronous counter, coupled to the control logic and the synchronous counter, having a chain of five DFFs.

REFERENCES:
patent: 4752592 (1988-06-01), Tamura et al.
patent: 5661675 (1997-08-01), Chin et al.
patent: 6060910 (2000-05-01), Inui
patent: 6385276 (2002-05-01), Hunt et al.
patent: 6462595 (2002-10-01), Hsu et al.
patent: 6737900 (2004-05-01), Wu
patent: 6759876 (2004-07-01), Inoue et al.
patent: 6822491 (2004-11-01), Glass
patent: 6919739 (2005-07-01), Ngo
patent: 6968029 (2005-11-01), Lee et al.
patent: 2002/0070758 (2002-06-01), Krishnamurthy et al.
patent: 2003/0141912 (2003-07-01), Sudjian
patent: 1469604 (2004-10-01), None
patent: 60-216629 (1985-10-01), None

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