Structure and method for local resistor element in...

Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics

Reexamination Certificate

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C257S213000, C257S288000, C257S368000, C257S499000, C257S528000, C257S536000, C257SE27009, C257S903000, C257S904000, C438S142000, C438S197000, C438S199000, C438S200000, C438S210000

Reexamination Certificate

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10708023

ABSTRACT:
A method and system for forming a semiconductor device having superior ESD protection characteristics. A resistive material layer is disposed within a contact hole on at least one of the contact stud upper and lower surface. In preferred embodiments, the integral resistor has a resistance value of between about one Ohm and about ten Ohms, or between 10 and 100 Ohms. Embodiments of the resistive layer include sputtered silicon material, a tunnel oxide, a tunnel nitride, a silicon-implanted oxide, a silicon-implanted nitride, or an amorphous polysilicon. Embodiments of the invention include SRAMs, bipolar transistors, SOI lateral diodes, MOSFETs and SiGe Transistors.

REFERENCES:
patent: 5232865 (1993-08-01), Manning et al.
patent: 5330930 (1994-07-01), Chi
patent: 5665629 (1997-09-01), Chen et al.
patent: 5930638 (1999-07-01), Reedy et al.
patent: 6117792 (2000-09-01), Kitagawa
patent: 6130462 (2000-10-01), Yang et al.
patent: 6297083 (2001-10-01), Klein
patent: 2002/0003311 (2002-01-01), Uematsu
patent: 2003/0116820 (2003-06-01), Daubenspeck et al.
patent: 4151825 (1992-05-01), None
“Vertically Integrated Load Resistor for MOS Static RAM Cells”, IBM Technical Disclosure Bulletin, vol. 26, No. 10B, Mar. 1984, pp. 5675-5677.

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