Tri-gate transistors and methods to fabricate same

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C438S254000, C257SE21540

Reexamination Certificate

active

10760028

ABSTRACT:
Embodiments of the invention provide a method for effecting uniform silicon body height for silicon-on-insulator transistor fabrication. For one embodiment, a sacrificial oxide layer is disposed upon a semiconductor substrate. The oxide layer is etched to form a trench. The trench is then filled with a semiconductor material. The semiconductor material is then planarized with the remainder of the oxide layer and the remainder of the oxide layer is then removed. The semiconductor fins thus exposed are of uniform height to within a specified tolerance.

REFERENCES:
patent: 4906589 (1990-03-01), Chao
patent: 5124777 (1992-06-01), Lee
patent: 5338959 (1994-08-01), Kim et al.
patent: 5346839 (1994-09-01), Sundaresan
patent: 5466621 (1995-11-01), Hisamoto et al.
patent: 5545586 (1996-08-01), Koh et al.
patent: 5563077 (1996-10-01), Ha
patent: 5578513 (1996-11-01), Maegawa
patent: 5658806 (1997-08-01), Lin et al.
patent: 5701016 (1997-12-01), Burroughs et al.
patent: 5716879 (1998-02-01), Choi et al.
patent: 5827769 (1998-10-01), Aminzadeh et al.
patent: 5888309 (1999-03-01), Yu
patent: 5905285 (1999-05-01), Gardner et al.
patent: 6114201 (2000-09-01), Wu
patent: 6163053 (2000-12-01), Kawashima
patent: 6252284 (2001-06-01), Muller et al.
patent: 6376317 (2002-04-01), Forbes et al.
patent: 6396108 (2002-05-01), Krivokapic et al.
patent: 6407442 (2002-06-01), Inoue et al.
patent: 6413802 (2002-07-01), Hu et al.
patent: 6413877 (2002-07-01), Annapragada
patent: 6475869 (2002-11-01), Yu
patent: 6475890 (2002-11-01), Yu
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6525403 (2003-02-01), Inaba et al.
patent: 6562665 (2003-05-01), Yu
patent: 6611029 (2003-08-01), Ahmed et al.
patent: 6635909 (2003-10-01), Clark et al.
patent: 6645797 (2003-11-01), Buynoski et al.
patent: 6680240 (2004-01-01), Maszara
patent: 6706571 (2004-03-01), Yu et al.
patent: 6709982 (2004-03-01), Buynoski et al.
patent: 6713396 (2004-03-01), Anthony
patent: 6716684 (2004-04-01), Krivokapic et al.
patent: 6716690 (2004-04-01), Wang et al.
patent: 6730964 (2004-05-01), Horiuchi
patent: 6756657 (2004-06-01), Zhang et al.
patent: 6764884 (2004-07-01), Yu et al.
patent: 6790733 (2004-09-01), Natzle et al.
patent: 6794313 (2004-09-01), Chang
patent: 6835618 (2004-12-01), Dakshina-Murthy et al.
patent: 6858478 (2005-02-01), Chau et al.
patent: 6884154 (2005-04-01), Mizushima et al.
patent: 6921982 (2005-07-01), Joshi et al.
patent: 2002/0011612 (2002-01-01), Hieda
patent: 2002/0036290 (2002-03-01), Inaba et al.
patent: 2002/0081794 (2002-06-01), Ito
patent: 2002/0166838 (2002-11-01), Nagarajan
patent: 2002/0167007 (2002-11-01), Yamazaki et al.
patent: 2003/0057486 (2003-03-01), Gambino et al.
patent: 2003/0085194 (2003-05-01), Hopkins, Jr.
patent: 2003/0098488 (2003-05-01), O'Keeffe et al.
patent: 2003/0102497 (2003-06-01), Fried et al.
patent: 2003/0111686 (2003-06-01), Nowak
patent: 2003/0122186 (2003-07-01), Sekigawa et al.
patent: 2003/0143791 (2003-07-01), Cheong et al.
patent: 2003/0151077 (2003-08-01), Mathew et al.
patent: 2003/0201458 (2003-10-01), Clark et al.
patent: 2003/0227036 (2003-12-01), Sugiyama et al.
patent: 2004/0031979 (2004-02-01), Lochtefeld et al.
patent: 2004/0036118 (2004-02-01), Adadeer et al.
patent: 2004/0036127 (2004-02-01), Chau et al.
patent: 2004/0092062 (2004-05-01), Ahmed et al.
patent: 2004/0092067 (2004-05-01), Hanafi et al.
patent: 2004/0094807 (2004-05-01), Chau et al.
patent: 2004/0110097 (2004-06-01), Ahmed et al.
patent: 2004/0119100 (2004-06-01), Nowak et al.
patent: 2004/0126975 (2004-07-01), Ahmed et al.
patent: 2004/0166642 (2004-08-01), Chen et al.
patent: 2004/0180494 (2004-09-01), Arai et al.
patent: 2004/0191980 (2004-09-01), Rios et al.
patent: 2004/0195624 (2004-10-01), Liu et al.
patent: 2004/0198003 (2004-10-01), Yeo et al.
patent: 2004/0219780 (2004-11-01), Ohuchi
patent: 2004/0227187 (2004-11-01), Cheng et al.
patent: 2004/0238887 (2004-12-01), Nihey
patent: 2004/0256647 (2004-12-01), Lee et al.
patent: 2004/0262683 (2004-12-01), Bohr et al.
patent: 2004/0262699 (2004-12-01), Rios et al.
patent: 2005/0035415 (2005-02-01), Yeo et al.
patent: 2005/0118790 (2005-06-01), Lee et al.
patent: 2005/0127362 (2005-06-01), Zhang et al.
patent: 2005/0145941 (2005-07-01), Bedell et al.
patent: 2005/0156171 (2005-07-01), Brask et al.
patent: 2005/0224797 (2005-10-01), Ko et al.
patent: 2005/0224800 (2005-10-01), Lindert et al.
patent: 0 623 963 (1994-11-01), None
patent: 1 202 335 (2002-05-01), None
patent: 1 566 422 (2005-08-01), None
patent: 06177089 (1994-06-01), None
patent: 2003298051 (2003-10-01), None
patent: WO 02/43151 (2002-05-01), None
patent: WO 2004/059726 (2004-07-01), None
International Search Report PCT/US2005/000947.
V. Subramanian et al., “A Bulk-Si-Compatible Ultrathin-body SOI Technology for Sub-100m MOSFETS” Proceeding of the 57th Annual Device Research Conference, pp. 28-29 (1999).
Hisamoto et al., “A Folded-channel MOSFET for Deepsub-tenth Micron Era”, 1998 IEEE International Electron Device Meeting Technical Digest, pp. 1032-1034 (1998).
Huang et al., “Sub 50-nm FinFET: PMOS”, 1999 IEEE International Electron Device Meeting Technical Digest, pp. 67-70 (1999).
Auth et al., “Vertical, Fully-Depleted, Surroundings Gate MOSFETS On sub-0.1um Thick Silicon Pillars”, 1996 54th Annual Device Research Conference Digest, pp. 108-109 (1996).
Hisamoto et al., “A Fully Depleted Lean-Channel Transistor (DELTA)-A Novel Vertical Ultrathin SOI MOSFET”, IEEE Electron Device Letters, V. 11(1), pp. 36-38 (1990).
Jong-Tae Park et al., “Pi-Gate SOI MOSFET” IEEE Electron Device Letters, vol. 22, No. 8, Aug. 2001, pp. 405-406.
Hisamoto, Digh et al. “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm”, IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
International Search Report PCT/US 03/26242.
International Search Report PCT/US 03/39727.
International Search Report PCT/US 03/40320.
International Search Report PCT/US2005/033439, mailed Jan. 31, 2006 (7 pgs.).
International Search Report PCT/US2005/035380, mailed Feb. 13, 2006 (14 pgs.).
International Search Report PCT/US2005/037169, mailed Feb. 23, 2006 (11 pgs.).
Sung Min Kim, et al., A Novel Multi-channel Field Effect Transistr (McFET) on Bulk Si for High Performance Sub-80nm Application, IEDM 04-639, 2004 IEEE, pp. 27.4.1-27.4.4.
Yang-Kyu Choi, et al., “A Spacer Patterning Technology for Nanoscale CMOS” IEEE Transactions on Electron Devices, vol. 49, No. 3, Mar. 2002, pp. 436-441.
W. Xiong, et al., “Corner Effect in Multiple-Gate SOI MOSFETs” 2003 IEEE, pp. 111-113.
Weize Xiong, et al., “Improvement of FinFET Electrical Characteristics by Hydrogen Annealing” IEEE Electron Device Letters, vol. 25, No. 8, Aug. 2004, XP-001198998, pp. 541-543.
Fu-Liang Yang, et al., “5nm-Gate Nanowire FinFET” 2004 Symposium on VLSI Technology Digest of Technical Papers, 2004 IEEE, pp. 196-197.
T. M. Mayer, et al., “Chemical Vapor Deposition of Fluoroalkylsilane Monolayer Films for Adhesion Control in Microelectromechanical Systems” 2000 American Vacuum Society B 18(5), Sep./Oct. 2000, pp. 2433-2440.
Jing Guo et al. “Performance Projections for Ballistic Carbon Nanotube Field-Effect Transistors” Applied Physics Letters, vol. 80, No. 17, Apr. 29, 2002, pp. 3192-2194.
Ali Javey et al., “High-K Dielectrics for Advanced Carbon-Nanotube Transistors and Logic Gates”, Advance Online Publication, Published online, Nov. 17, 2002 pp. 1-6.
Richard Martel et al., “Carbon Nanotube Field Effect Transistors for Logic Applications” IBM, T.J. Watson Research Center, 2001 IEEE, IEDM 01, pp. 159-162.
David M. Fried et al., “Improved Independent Gate N-Type FinFET Fabrication and Characterization”, IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003, pp. 592-594.
David M. Fried et al., “Improved Independent Gate P-Type Independent-Gate FinFETs”, IEEE Electron Device Letters, vol

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Tri-gate transistors and methods to fabricate same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Tri-gate transistors and methods to fabricate same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Tri-gate transistors and methods to fabricate same will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3761268

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.