Method for reducing drain disturb in programming

Details Method for reducing drain disturb in programming Method for reducing drain disturb in programming

Filed on

2007-05-08

Date issued

2007-05-08

Examiner

Dinh, Son (Department: 2824)

Patent Class

Static information storage and retrieval

SubClass

Floating gate

Other Related Categories

C365S185140, C365S185330

Type

Reexamination Certificate

Status

active

Patent number

10931689

Description

ABSTRACT:
For a multi-sectored flash memory array with bitlines spanning multiple erase blocks, a bias scheme for programming an address in any erase sector while minimizing drain voltage induced disturb to cells in unselected erase sectors sharing the same bitlines.

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