Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257SE21589, C257SE29112, C257S059000, C257S072000, C438S296000, C438S665000

Reexamination Certificate

active

10976882

ABSTRACT:
A technology for easily forming a multi-layer wiring structure that is fine and reliable. In the multi-layer wiring structure, the lower-layer wiring and the upper-layer wiring that are formed to sandwich an insulating layer are electrically connected to each other in a projection formed in the lower-layer wiring. The projection includes a columnar conductive member and the upper and lower layers thereof and each of the lower layer and the upper layer is formed of a conductive layer formed over the entire lower-layer wiring. The upper-layer is electrically connected to the lower-layer wiring in the portion where the projection is exposed substantially on the same plane as the top surface of the insulating layer.

REFERENCES:
patent: 5202579 (1993-04-01), Fujii et al.
patent: 5290729 (1994-03-01), Hayashide et al.
patent: 5313101 (1994-05-01), Harada et al.
patent: 5341026 (1994-08-01), Harada et al.
patent: 5554888 (1996-09-01), Kato
patent: 5665642 (1997-09-01), Kato
patent: 5801093 (1998-09-01), Lin
patent: 6400031 (2002-06-01), Harada
patent: 2004/0090175 (2004-05-01), Urabe et al.
patent: 2004/0125265 (2004-07-01), Koo et al.
patent: 2005/0200300 (2005-09-01), Yumoto
patent: 2005/0282304 (2005-12-01), Inoue et al.
patent: 06-314687 (1994-11-01), None
patent: 08-306779 (1996-11-01), None

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