Method and apparatus for executing a 32-bit application by...

Electrical computers and digital processing systems: processing – Instruction decoding – Decoding instruction to accommodate plural instruction...

Reexamination Certificate

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C711S212000

Reexamination Certificate

active

09536452

ABSTRACT:
Apparatus and methods to execute an instruction of an application of a first bit size ported to a second bit size environment, including methods and apparatus to confine the application to a first bit size address space subset. An embodiment in accordance with the present invention includes a method to confine an application to an address space subset, the method including determining that the application is confined to a first bit size address subset, the application including an instruction; generating an address reference of a second bit size as part of execution of the instruction; truncating the generated address reference from the second bit size to the first bit size; and extending the truncated, generated address reference from the first bit size to the second bit size based at least in part on an address format control flag.

REFERENCES:
patent: 5140684 (1992-08-01), Sakamura et al.
patent: 5420992 (1995-05-01), Killian et al.
patent: 5638525 (1997-06-01), Hammond et al.
patent: 5774686 (1998-06-01), Hammond et al.
Hennessy and Patterson, Computer Architecture—A Quantitative Approach, 2nd Edition, p. A-8 to A-11.
Microsoft Corporation, “Microsoft Interface Definition Language (MIDL): 64-Bit Porting Guide,” Aug. 1999, pp. 1-19.
Intel Architecture Software Developer's Manual, Basic Architecture, vol. 1, pp. 2-1-2-13, 1999.

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