Semiconductor memory device and method of production

Details Semiconductor memory device and method of production Semiconductor memory device and method of production

2007-07-17

2007-07-17

Lee, Calvin (Department: 2818)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

C257S390000

Reexamination Certificate

active

11241820

ABSTRACT:
Final sections of the word lines are arranged in a staggered fashion to fan out and have larger lateral extensions than the word lines. Interspaces are filled with a dielectric material, and a mask is applied that partially covers the final sections and leaves contact areas in regions adjacent to the final sections and to the interspaces open. This mask is used to remove the dielectric material between the word line stacks. A second word line layer is applied and planarized to form second word lines between the first word lines, which have contact areas arranged in a staggered fashion to fan out like the final sections of the first word lines.

REFERENCES:
patent: 6445046 (2002-09-01), Hofmann et al.
patent: 2003/0234449 (2003-12-01), Aratani et al.
patent: 2005/0029681 (2005-02-01), Ishii et al.
patent: 2005/0189570 (2005-09-01), Nomoto et al.
patent: 196 52 547 (1998-06-01), None

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