Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2007-05-08
2007-05-08
Dinh, Son (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S203000, C365S230080, C365S189050
Reexamination Certificate
active
11560650
ABSTRACT:
A semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix form, a plurality of word lines connected to the memory cells, a row decoder including a plurality of decode sections and configured to receive first and second address signals for selecting the word lines, each of the decode sections which is provided for a respective one of the word lines, and includes first and second MOS transistors connected in series, the first MOS transistor having its gate electrode connected to receive the first address signal, the second MOS transistor having its gate electrode connected to receive the second address signal, the row decoder outputting a first signal for controlling the word lines, and a control circuit which delays the second address signal in time with respect to the first address signal.
REFERENCES:
patent: 6081452 (2000-06-01), Ohta
patent: 6614711 (2003-09-01), Schreck
patent: 6621745 (2003-09-01), Manea
patent: 6847563 (2005-01-01), Koshikawa
patent: 2002-63795 (2002-02-01), None
Daisaburo Takashima, et al., “A Cell Transistor Scalable Array Architecture for High-Density DRAMs”, 2001 Symposium on VLSI Circuits Digest of Technical Papers, 2001, pp. 31-32.
Dinh Son
Kabushiki Kaisha Toshiba
Nguyen N
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