Method of manufacturing semiconductor devices

Active solid-state devices (e.g. – transistors – solid-state diode – Non-single crystal – or recrystallized – semiconductor... – Amorphous semiconductor material

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S059000, C257S072000, C257S083000, C257S257000, C257S292000, C257S412000

Reexamination Certificate

active

10973868

ABSTRACT:
Subjected to obtain a crystalline TFT which simultaneously prevents increase of OFF current and deterioration of ON current. A gate electrode of a crystalline TFT is comprised of a first gate electrode and a second gate electrode formed in contact with the first gate electrode and a gate insulating film. LDD region is formed by using the first gate electrode as a mask, and a source region and a drain region are formed by using the second gate electrode as a mask. By removing a portion of the second gate electrode, a structure in which a region where LDD region and the second gate electrode overlap with a gate insulating film interposed therebetween, and a region where LDD region and the second gate electrode do not overlap, is obtained.

REFERENCES:
patent: 3933529 (1976-01-01), Goser
patent: 4727038 (1988-02-01), Watabe et al.
patent: 5247190 (1993-09-01), Friend et al.
patent: 5323042 (1994-06-01), Matsumoto
patent: 5399502 (1995-03-01), Friend et al.
patent: 5523257 (1996-06-01), Yamazaki et al.
patent: 5594569 (1997-01-01), Konuma et al.
patent: 5643826 (1997-07-01), Ohtani et al.
patent: 5693959 (1997-12-01), Inoue et al.
patent: 5719588 (1998-02-01), Johnson
patent: 5736750 (1998-04-01), Yamazaki et al.
patent: 5742363 (1998-04-01), Bae
patent: 5891766 (1999-04-01), Yamazaki et al.
patent: 5912492 (1999-06-01), Chang et al.
patent: 5923962 (1999-07-01), Ohtani et al.
patent: 6078060 (2000-06-01), Shibuya et al.
patent: 6096585 (2000-08-01), Fukuda et al.
patent: 6114728 (2000-09-01), Yamazaki et al.
patent: 6166396 (2000-12-01), Yamazaki
patent: 6180957 (2001-01-01), Miyasaka et al.
patent: 6198133 (2001-03-01), Yamazaki et al.
patent: 6242290 (2001-06-01), Nakajima et al.
patent: 6281552 (2001-08-01), Kawasaki et al.
patent: 6417543 (2002-07-01), Yamazaki et al.
patent: 6518594 (2003-02-01), Nakajima et al.
patent: 6670641 (2003-12-01), Fukuda et al.
patent: 6984551 (2006-01-01), Yamazaki et al.
patent: 2002/0123179 (2002-09-01), Yamazaki et al.
patent: 2004/0051142 (2004-03-01), Yamazaki et al.
patent: 2006/0081931 (2006-04-01), Yamazaki et al.
patent: 03-250632 (1991-11-01), None
patent: 04-165629 (1992-06-01), None
patent: 04-369271 (1992-12-01), None
patent: 05-102483 (1993-04-01), None
patent: 06-216156 (1994-08-01), None
patent: 06-260645 (1994-09-01), None
patent: 07-130652 (1995-05-01), None
patent: 08-078329 (1996-03-01), None
patent: 10-092576 (1998-04-01), None
patent: 10-135468 (1998-05-01), None
patent: 10-135469 (1998-05-01), None
patent: 10-163498 (1998-06-01), None
patent: 10-189979 (1998-07-01), None
patent: 10-247735 (1998-09-01), None
patent: WO 90/13148 (1990-11-01), None
Inuni, S. et al, “Thresholdless Antiferroelectricity in Liquid Crystals and its Application to Displays,” J. Mater Chem., vol. 6, No. 4, pp. 671-673 (1996).
Yoshida, T. et al, “A Full-Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time,” SID 97 Digest, pp. 841-844 (1997).
Furue, H. et al, “Characteristics and Driving Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability,” SID 98 Digest, pp. 782-785 (1998).
Terada, et al, “Half-V Switching Mode FLCD,” Proceedings of the 46th Applied Physics Association Lectures, 28p-V-8, p. 1316, Mar. (1999).
Yoshihara, T. et al, “Time Division Full Color LCD by Ferroelectric Liquid Crystal,” EKISHO, vol. 3, No. 3, pp. 190-194 (1999).
Hatano, M. et al, “A Novel Self-Aligned Gate-Overlapped LDD Poly-Si TFT with High Reliability and Performance,” IEDM 97, pp. 523-526 (1997).
Schenk, H. et al, “Polymers for Light Emitting Diodes,” EuroDisplay '99 Proceedings of the 19th International Display Research Conference, Berlin, Germany, Sep. 6-9, 1999, pp. 33-37 (1999).
U.S. Appl. No. 09/432,662, to Yamazaki et al filed Nov. 3, 1999, including specification, claims, abstract, drawings and PTO filing receipt.
U.S. Appl. No. 09/435,154, to Yamazaki et al filed Nov. 8, 1999, including specification, claims, abstract, drawings and PTO filing receipt.
Definition of “Overlap” from Webster's II Dictionary, p. 839.
Claims of 10/640,939, (after amendment of Apr. 24, 2006 in response to the Office Action of Jan. 23, 2006).
Definiton of “Overlap” from Webster's II Dictionary, p. 839 (1984).

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method of manufacturing semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of manufacturing semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing semiconductor devices will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3755927

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.