Flipflop that can tolerate arbitrarily slow clock edges

Details Flipflop that can tolerate arbitrarily slow clock edges Flipflop that can tolerate arbitrarily slow clock edges

2007-09-04

2007-09-04

Wells, Kenneth B. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000, C327S212000, C327S215000, C327S218000

Reexamination Certificate

active

10997290

ABSTRACT:
A edge triggered flipflop tolerates arbitrarily slow clock edge rates by utilizing complex gates, with weighted transistors, to electrically isolate the master latch from the data inputs, before the master latch and the slave latch are electrically connected together, and to electrically isolate the master latch from the slave latch, before the master latch and the data inputs are electrically connected together.

REFERENCES:
patent: 3467839 (1969-09-01), Miller
patent: 3609569 (1971-09-01), Todd
patent: 4002933 (1977-01-01), Leuschner
patent: 4209715 (1980-06-01), Aoki
patent: 5324996 (1994-06-01), Mote, Jr.
patent: 5781053 (1998-07-01), Ramirez

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