Multiple level cell memory device with single bit per cell,...

Details Multiple level cell memory device with single bit per cell,... Multiple level cell memory device with single bit per cell,...

2007-05-15

2007-05-15

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S200000, C365S201000, C365S185170

Reexamination Certificate

active

11417572

ABSTRACT:
A non-volatile memory device has a plurality of memory cells that are organized into memory blocks. Each block can operate in either a multiple level cell mode or a single bit per cell mode. One dedicated memory block is capable of operating only in the single bit per cell mode. If the dedicated memory block is found to be defective, a defect-free block can be remapped to that dedicated memory block location to act only in the single bit per cell mode.

REFERENCES:
patent: 5877986 (1999-03-01), Harari
patent: 6414876 (2002-07-01), Harari
patent: 6462992 (2002-10-01), Harari
patent: 6519185 (2003-02-01), Harari
patent: 6523132 (2003-02-01), Harari
patent: 6697290 (2004-02-01), Koss et al.

Affiliated with

Also associated with

Rating

Multiple level cell memory device with single bit per cell,... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple level cell memory device with single bit per cell,..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple level cell memory device with single bit per cell,... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3752927