Polycarbosilane buried etch stops in interconnect structures

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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C257S774000, C438S970000

Reexamination Certificate

active

10699238

ABSTRACT:
Interconnect structures having buried etch stop layers with low dielectric constants and methods relating to the generation of such buried etch stop layers are described herein. The inventive interconnect structure comprises a buried etch stop layer comprised of a polymeric material having a composition SivNwCxOyHz, where 0.05≦v≦0.8, 0≦w≦0.9, 0.05≦x≦0.8, 0≦y≦0.3, 0.05≦z≦0.8 for v+w+x+y+z=1; a via level interlayer dielectric that is directly below said buried etch stop layer; a line level interlayer dielectric that is directly above said buried etch stop layer; and conducting metal features that traverse through said via level dielectric, said line level dielectric, and said buried etch stop layer.

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patent: 6162743 (2000-12-01), Chu et al.
patent: 6395649 (2002-05-01), Wu
patent: 6893955 (2005-05-01), Lopatin et al.
patent: 2002/0172898 (2002-11-01), Forester
patent: 2003/0017635 (2003-01-01), Apen et al.
patent: 2005/0124153 (2005-06-01), Cohen

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