Cyclic resynchronization marker for error tolerate video coding

Details Cyclic resynchronization marker for error tolerate video coding Cyclic resynchronization marker for error tolerate video coding

2007-07-10

2007-07-10

Philippe, Gims (Department: 2621)

Pulse or digital communications

Bandwidth reduction or expansion

Television or motion video signal

C382S236000

Reexamination Certificate

active

10284218

ABSTRACT:
A system and method are disclosed that provide an advanced design of coded video packets using a resynchronization maker for video transmission applications. The resynchronization marker has a fixed ranged bit length within each video object plane or video frame and is cyclically updated video frame by video frame. This coded video packet structure allows decoders to automatically find the video object plane boundary without additional bit stream overhead. This has a particular advantage when a video object plane header is lost during transmission.

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patent: 200036760 (2000-02-01), None

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