Electronic device and method for designing the same

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means

Reexamination Certificate

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Details

C257S202000, C257S797000, C257S798000, C257S401000, C438S800000

Reexamination Certificate

active

11081727

ABSTRACT:
The electronic device includes a plurality of layout regions each including a plurality of patterns defined by a buried structure buried in a substrate. For each of the layout regions, in each of the layout regions, the minimum space between the patterns, and a maximum area percentage allowed for the patterns in the layout region are defined based on a size of the layout region. In larger one of the layout regions, the minimum space between the patterns in the region is set larger.

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