Non-volatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185110, C365S185290

Reexamination Certificate

active

10957826

ABSTRACT:
A semiconductor memory device including: a cell array with electrically rewritable and non-volatile memory cells arranged therein; a sense amplifier circuit configured to read data of and write data into the cell array; and a controller configured to control read, write and erase of the cell array, wherein the controller executes an erase sequence for erasing a selected block in the cell array in response to erase command and address input in such a way of: executing a first erase-verify operation for verifying an erase state of the selected block; ending the erase sequence if the erase state of the selected block has been verified by the first erase-verify operation; whereas executing an erase operation for the selected block if the erase state has not been verified.

REFERENCES:
patent: 6421276 (2002-07-01), Goltman
patent: 6717858 (2004-04-01), Kawai et al.
patent: 6903981 (2005-06-01), Futatsuyama et al.
patent: 2003/0169630 (2003-09-01), Hosono et al.
patent: 2003-22681 (2003-01-01), None

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