Method for reducing critical dimension and semiconductor...

Details Method for reducing critical dimension and semiconductor... Method for reducing critical dimension and semiconductor...

2007-09-11

2007-09-11

Vinh, Lan (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S706000, C438S710000, C216S058000

Reexamination Certificate

active

11161996

ABSTRACT:
A method of reducing critical dimension is provided. A dielectric layer is formed on a substrate. Then, a patterned photoresist is formed on the dielectric layer to expose part of the dielectric layer, wherein the patterned photoresist has a first line width. An etching process is performed to remove the exposed dielectric layer by using the patterned photoresist as an etching mask, wherein the final line width of the dielectric layer is smaller than the first line width. The conditions of the etching process include an etching pressure at 80 torr to 400 torr, an etching gas that includes a fluorocarbon compound and oxygen, wherein the ratio of the fluorocarbon compound to the oxygen is large than 0 and less than 10. Consequently, the etching process can be stabilized to form a smooth sidewall for the gate and to provide a uniform critical dimension.

REFERENCES:
patent: 6106659 (2000-08-01), Spence et al.
patent: 6372651 (2002-04-01), Yang et al.
patent: 7091104 (2006-08-01), Kim et al.
patent: 2001/0017286 (2001-08-01), Zanotti

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