Methods of fabricating ESD protection structures

Details Methods of fabricating ESD protection structures Methods of fabricating ESD protection structures

2007-03-27

2007-03-27

Tsai, H. Jety (Department: 2812)

Semiconductor device manufacturing: process

Making regenerative-type switching device

C438S134000, C257S029000

Reexamination Certificate

active

10882874

ABSTRACT:
The present invention provides a novel ESD structure for protecting an integrated circuit (IC) from ESD damage and a method of fabricating the ESD structure on a semiconductor substrate. The ESD structure of the present invention has lower trigger voltage and lower capacitance, and takes smaller substrate area than prior art ESD structures. The low trigger voltage is provided by a small N+P diode or a P+N diode which has a PN junction with a much lower breakdown voltage than a PN junction between a N+ (or P+) source/drain region and a P-well (or N-well). All of the diffusion regions in the ESD device of the present invention can be formed using ordinary process steps for fabricating the MOS devices in the IC and does not require extra masking steps in addition to those required to fabricate the IC.

REFERENCES:
patent: 6630377 (2003-10-01), Panday et al.

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