Processor with a replay system that includes a replay queue...

Details Processor with a replay system that includes a replay queue... Processor with a replay system that includes a replay queue...

2007-04-03

2007-04-03

Donaghue, Larry D. (Department: 2154)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Commitment control or register bypass

C712S219000, C712S023000

Reexamination Certificate

active

09474096

ABSTRACT:
A processor is provided that includes an execution unit for executing instructions and a replay system for replaying instructions which have not executed properly. The replay system is coupled to the execution unit and includes a checker for determining whether each instruction has executed properly and a replay queue coupled to the checker for temporarily storing one or more instructions for replay. The replay queue may be used to store a long latency instruction, such as a load in which data must be retrieved from an external memory device. The long latency instruction and possibly one or more dependent instruction are stored in the replay queue until the long latency instruction is ready to be executed (e.g., data for the load instruction has been retrieved from external memory). Once the long latency instruction is ready to be executed, (e.g., the data is available), the long latency instruction may then be unloaded from the replay queue for re-execution.

REFERENCES:
patent: 5197132 (1993-03-01), Steely, Jr. et al.
patent: 5519841 (1996-05-01), Sager et al.
patent: 5966544 (1999-10-01), Sager
patent: 6094717 (2000-07-01), Merchant et al.
patent: 6385715 (2002-05-01), Merchant et al.

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