Multiple phase detection for delay loops

Details Multiple phase detection for delay loops Multiple phase detection for delay loops

2007-05-01

2007-05-01

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S156000, C327S161000

Reexamination Certificate

active

11138703

ABSTRACT:
A circuit (e.g., a receiver) has a delay loop (e.g., a voltage-controlled delay loop) and (at least) two phase detectors (PDs), where each PD compares a different pair of clock signals generated by the delay loop. The outputs of the different PDs are then used to generate a control signal for adjusting the delays provided by the delay elements in the delay loop. In one implementation, the control signal indicates that a delay adjustment should be made only if both PDs agree on that adjustment. This multiple-PD technique can reduce jitter that could otherwise result from a non-50% duty cycle in the reference clock signal used by the delay loop to generate its multiple clock signals.

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